CPC H04L 47/122 (2013.01) [H04L 47/29 (2013.01); H04L 47/326 (2013.01); H04L 47/521 (2013.01)] | 21 Claims |
1. An apparatus, comprising:
on-chip memory configured to store packets in queues; and
a processor configured to, in response to determining that a source device is unresponsive to a congestion notification, reduce a size of one or more queues to prevent packets transferring from the on-chip memory to an external memory.
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