US 11,895,029 B2
Network processor with external memory protection
Brian Alleyne, Los Gatos, CA (US); Matias Cavuoti, San Jose, CA (US); Li-Chuan Egan, Los Altos, CA (US); Mimi Dannhardt, Vienna, VA (US); Krishnan Subramani, San Jose, CA (US); Mohamed Abdul Malick Mohamed Usman, Fremont, CA (US); Roxanna Ganji, Fremont, CA (US); and Stephen Russell, Linden, CA (US)
Assigned to Nokia Solutions and Networks Oy, Espoo (FI)
Filed by NOKIA SOLUTIONS AND NETWORKS OY, Espoo (FI)
Filed on Dec. 10, 2021, as Appl. No. 17/548,451.
Prior Publication US 2023/0188467 A1, Jun. 15, 2023
Int. Cl. H04L 47/00 (2022.01); H04L 47/122 (2022.01); H04L 47/10 (2022.01); H04L 47/52 (2022.01); H04L 47/32 (2022.01)
CPC H04L 47/122 (2013.01) [H04L 47/29 (2013.01); H04L 47/326 (2013.01); H04L 47/521 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
on-chip memory configured to store packets in queues; and
a processor configured to, in response to determining that a source device is unresponsive to a congestion notification, reduce a size of one or more queues to prevent packets transferring from the on-chip memory to an external memory.