US 11,894,959 B2
Ultra-high-speed PAM-N CMOS inverter serial link
Ronan Sean Casey, Cork (IE); Lokesh Rajendran, Cork (IE); Declan Carey, Douglas (IE); Kevin Zheng, San Jose, CA (US); Catherine Hearne, Fermoy (IE); and Hongtao Zhang, San Jose, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Jul. 25, 2022, as Appl. No. 17/873,002.
Application 17/873,002 is a continuation of application No. 17/478,883, filed on Sep. 18, 2021, granted, now 11,398,934.
Prior Publication US 2023/0089431 A1, Mar. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04L 25/49 (2006.01); H04L 27/04 (2006.01)
CPC H04L 25/4917 (2013.01) [H04L 27/04 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A transmitter circuit comprising:
two or more input converter circuits coupled in parallel, each of the two or more input converter circuits configured to convert a non-return-to-zero (NRZ) input voltage signal to a corresponding current signal; and
a combining circuit, the combining circuit configured to combine the two or more corresponding current signals to generate a pulse amplitude modulation level N (PAM-N) signal output,
wherein the two or more input converter circuits and the combining circuit comprise a CMOS-inverter-based circuit.