CPC H04L 1/0041 (2013.01) [H03M 13/05 (2013.01); H03M 13/1515 (2013.01); H03M 13/27 (2013.01); H03M 13/3761 (2013.01); H03M 13/6561 (2013.01); H04J 13/004 (2013.01); H04L 1/0071 (2013.01); H04L 25/0272 (2013.01); H04L 25/085 (2013.01)] | 35 Claims |
1. A method comprising:
obtaining a set of information bits;
sequentially allocating data bytes of the set of information bits to respective forward error correction (FEC) encoders of a plurality of parallel FEC encoders to generate a plurality of parallel FEC-encoded data bytes;
providing, in a first interleaved order, a first set of FEC-encoded data bytes obtained from the plurality of parallel FEC-encoded data bytes to respective transport channels of a plurality of transport channels of an analog physical layer (PHY) circuit for parallel transmission during a plurality of signaling intervals; and
providing, in a second interleaved order, a second set of FEC-encoded data bytes obtained from the plurality of parallel FEC-encoded data bytes to respective transport channels of the plurality of transport channels for parallel transmission during a subsequent plurality of signaling intervals.
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