US 11,894,840 B2
Output buffer for a swappable single conductor interface
Robert Mark Englekirk, Littleton, CO (US); Keith Rampmeier, San Diego, CA (US); and Arpita Moghe Chadha, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Apr. 1, 2022, as Appl. No. 17/711,845.
Prior Publication US 2023/0318598 A1, Oct. 5, 2023
Int. Cl. H03K 17/693 (2006.01); H03K 19/17736 (2020.01); H03K 19/0944 (2006.01); G06F 13/42 (2006.01); G06F 13/40 (2006.01)
CPC H03K 17/693 (2013.01) [H03K 19/0944 (2013.01); H03K 19/17744 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An output buffer for a swappable single conductor interface having a first pin and a second pin, wherein either of the first pin or second pins is couplable to an input/output line or to an external capacitor line, the output buffer including:
(a) a first transistor having a conduction channel coupled between the first pin and a reference potential, and configured to be selectively operable in response to a pin-connection flag signal having a first state and non-operable in response to the pin-connection flag signal having a second state;
(b) a second transistor having a conduction channel coupled between the second pin and the reference potential, and configured to be selectively operable in response to the pin-connection flag signal having the second state and non-operable in response to the pin-connection flag signal having the first state; and
(c) a third transistor having a conduction channel coupled between the first and second pins, and configured to be selectively operable;
wherein the operable third transistor and the operable one of the first and second transistors have complementary ON or OFF conductive states in response to applied command and data signals;
wherein the coupled input/output line is connected to the coupled external capacitor line through the operable third transistor when the operable third transistor is set to the ON conductive state; and
wherein the first state of the pin-connection flag signal indicates that the second pin is coupled to a storage capacitor, and the second state of the pin-connection flag signal indicates that the first pin is coupled to the storage capacitor.