CPC H01L 29/78609 (2013.01) [H01L 29/0653 (2013.01); H01L 29/0673 (2013.01); H01L 29/0676 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/785 (2013.01); H01L 29/78606 (2013.01); H01L 29/78618 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A non-planar semiconductor device, comprising:
a hetero-structure disposed above a substrate, the hetero-structure comprising a hetero junction between an upper layer and a lower layer of differing composition;
an active layer disposed above the hetero-structure and having a composition different from the upper and lower layers of the hetero-structure;
a gate structure disposed on and surrounding a channel region of the active layer, and disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure;
one or more nanowires disposed in a vertical arrangement above the active layer, wherein the gate structure is disposed on and surrounds each of the nanowires;
source and drain regions disposed on the substrate and in the upper layer on either side of the gate structure; and
isolation regions adjacent the source and drain regions and disposed at least partially into the hetero-structure.
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