US 11,894,442 B2
Full nanosheet airgap spacer
Jingyun Zhang, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Reinaldo Vega, Mahopac, NY (US); Kangguo Cheng, Schenectady, NY (US); and Lan Yu, Voorheesville, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,275.
Prior Publication US 2022/0416056 A1, Dec. 29, 2022
Int. Cl. H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01)
CPC H01L 29/6653 (2013.01) [H01L 29/0653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/66742 (2013.01); H01L 29/78696 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A nanosheet transistor for reducing parasitic capacitance, comprising:
a spacer region between a high-k metal gate and an epitaxial layer, wherein the spacer region comprises:
a first nanosheet stack comprising a first nanosheet and a second nanosheet;
an inner spacer region between the first nanosheet and the second nanosheet; and
a side subway region located along an edge of the first nanosheet, the inner spacer region, and the second nanosheet, wherein the side subway region contacts a shallow trench isolation below the spacer region.