US 11,894,433 B2
Method and structure to improve stacked FET bottom EPI contact
Alexander Reznicek, Troy, NY (US); Ruilong Xie, Niskayuna, NY (US); Chen Zhang, Guilderland, NY (US); and Kangguo Cheng, Schenectady, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Jun. 22, 2021, as Appl. No. 17/304,461.
Prior Publication US 2022/0406908 A1, Dec. 22, 2022
Int. Cl. H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01)
CPC H01L 29/41733 (2013.01) [H01L 29/0665 (2013.01); H01L 29/401 (2013.01); H01L 29/42392 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A stacked semiconductor device comprising:
a lower source/drain epi located on top of a bottom dielectric layer;
an isolation layer located on top of the lower source/drain epi;
an upper source/drain epi located on top of the isolation layer; and
a lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi, wherein the lower electrical contact extends under the lower source/drain epi.