	US 11,894,425 B2
	Semiconductor arrangement and method of manufacture
Yun-Chi Wu, Tainan (TW); Tsung-Yu Yang, Tainan (TW); Cheng-Bo Shu, Tainan (TW); and Chien Hung Liu, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsin-Chu (TW)
Filed on Feb. 6, 2023, as Appl. No. 18/106,001.
Application 18/106,001 is a continuation of application No. 17/098,751, filed on Nov. 16, 2020, granted, now 11,575,008.
Application 17/098,751 is a continuation of application No. 16/371,535, filed on Apr. 1, 2019, granted, now 10,840,333, issued on Nov. 17, 2020.
Claims priority of provisional application 62/753,152, filed on Oct. 31, 2018.
Prior Publication US 2023/0187499 A1, Jun. 15, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 21/3213 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/311 (2006.01); H01L 29/66 (2006.01); H01L 21/027 (2006.01); H01L 21/8238 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 21/02 (2006.01); H10B 10/00 (2023.01)

CPC H01L 29/0847 (2013.01) [H01L 21/0276 (2013.01); H01L 21/02164 (2013.01); H01L 21/266 (2013.01); H01L 21/2652 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/32136 (2013.01); H01L 21/32139 (2013.01); H01L 21/823814 (2013.01); H01L 21/823828 (2013.01); H01L 27/092 (2013.01); H01L 29/401 (2013.01); H01L 29/6656 (2013.01); H01L 29/6659 (2013.01); H01L 29/66545 (2013.01); H01L 29/7833 (2013.01); H10B 10/12 (2023.02)]

20 Claims

1. A semiconductor arrangement, comprising:

a first transistor, comprising a first gate structure; and

a second transistor, comprising a second gate structure, wherein the second gate structure contacts the first gate structure such that an interface is defined between the first gate structure and the second gate structure and a center of the second gate structure is laterally offset from a center of the first gate structure at the interface.