US 11,894,420 B2
Memory and formation method thereof
Qiang Zhang, Hefei (CN); and Zhan Ying, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC.
Filed on Jul. 27, 2021, as Appl. No. 17/386,492.
Application 17/386,492 is a continuation of application No. PCT/CN2020/104961, filed on Jul. 27, 2020.
Claims priority of application No. 201911087493.6 (CN), filed on Nov. 8, 2019.
Prior Publication US 2021/0359084 A1, Nov. 18, 2021
Int. Cl. H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 27/105 (2023.01); H10B 99/00 (2023.01)
CPC H01L 29/0649 (2013.01) [H01L 21/76224 (2013.01); H01L 27/105 (2013.01); H10B 99/00 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A memory, comprising:
a substrate, comprising an array area and a peripheral area encircling the array area; and
a plurality of discrete active areas arranged in staggered rows and located in the array area; and, wherein
a first-positioned discrete active area, in each row of a first plurality of adjacent rows, contacts the substrate of the peripheral area at a first side of the array area;
a first-positioned discrete active area, in each row of a second plurality of adjacent rows, contacts the substrate of the peripheral area at a second side of the array area that intersects the first side of the array area; and
the discrete active areas are separated from each other by a shallow trench isolation structure;
wherein a last-positioned discrete active area, in each row of the first plurality of adjacent rows, contacts the substrate of the peripheral area; and
a last-positioned discrete active area, in each row of the second plurality of adjacent rows, contacts the substrate of the peripheral area.