US 11,894,410 B2
Bond pad structure for bonding improvement
Sin-Yao Huang, Tainan (TW); Ching-Chun Wang, Tainan (TW); Dun-Nian Yaung, Taipei (TW); Feng-Chi Hung, Chu-Bei (TW); Ming-Tsong Wang, Taipei (TW); and Shih Pei Chou, Tainan (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Feb. 1, 2022, as Appl. No. 17/590,224.
Application 16/043,919 is a division of application No. 15/088,232, filed on Apr. 1, 2016, granted, now 10,038,026, issued on Jul. 31, 2018.
Application 17/590,224 is a continuation of application No. 16/705,376, filed on Dec. 6, 2019, granted, now 11,244,981.
Application 16/705,376 is a continuation of application No. 16/043,919, filed on Jul. 24, 2018, granted, now 10,515,995, issued on Dec. 24, 2019.
Claims priority of provisional application 62/184,608, filed on Jun. 25, 2015.
Prior Publication US 2022/0157864 A1, May 19, 2022
Int. Cl. H01L 27/146 (2006.01)
CPC H01L 27/1464 (2013.01) [H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a first substrate including a plurality of imaging devices;
a second substrate disposed under the first substrate and including a plurality of logic devices;
a first interconnect structure disposed between the first substrate and the second substrate and configured to electrically couple imaging devices within the first substrate to one another;
a second interconnect structure disposed between the first interconnect structure and the second substrate, the second interconnect structure configured to electrically couple logic devices within the second substrate to one another;
a bond pad structure coupled to a metal layer of the second interconnect structure and extending along inner sidewalls of both the first interconnect structure and the second interconnect structure; and
an oxide layer extending from above the first substrate to below a plurality of metal layers of the first interconnect structure, and lining inner sidewalls of the bond pad structure.