CPC H01L 27/14605 (2013.01) [G01S 11/00 (2013.01); G01S 17/894 (2020.01); H01L 27/1463 (2013.01); H01L 27/14609 (2013.01); H01L 27/14643 (2013.01); H04N 23/60 (2023.01); H04N 23/73 (2023.01); H04N 25/40 (2023.01); H04N 25/77 (2023.01); H04N 25/771 (2023.01); H04N 25/778 (2023.01); H01L 27/14641 (2013.01)] | 18 Claims |
1. An image sensor device comprising:
a plurality of pixel cells arranged in a pixel array, wherein the plurality of pixel cells comprises a first plurality of odd pixel cells and a second plurality of even pixel cells;
a control circuit configured to control an exposure phase and a sampling phase of the image sensor device; and
a switching circuit configured to couple a pixel power supply line to a first voltage in the exposure phase and to a second voltage in the sampling phase, the first voltage being higher than the second voltage;
wherein each of the plurality of pixel cells comprises:
a photodiode in a semiconductor substrate, wherein a first end of the photodiode is coupled to a bias voltage through a shutter gate controlled by a global shutter signal;
a ground contact configured to couple a second end of the photodiode to an electrical ground through an electrical ground line;
a storage diode in the semiconductor substrate and coupled to the second end of the photodiode through a first transfer gate controlled by a first transfer signal;
a floating diffusion region in the semiconductor substrate and coupled to the storage diode through a second transfer gate controlled by a second transfer signal; and
a select transistor configured to couple to a bit line circuit coupled to the control circuit,
wherein the bit line circuit comprises an odd bit line coupled to the first plurality of odd pixel cells and an even bit line coupled to the second plurality of even pixel cells.
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