CPC H01L 27/1211 (2013.01) [H01L 21/845 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01)] | 20 Claims |
1. A method for manufacturing a semiconductor structure, comprising:
forming a fin structure over a substrate;
forming a source/drain of a first transistor, a source/drain of a second transistor and a first semiconductive component in the fin structure of the substrate at a first elevation, wherein the first semiconductive component is adjacent to the source/drain of the second transistor;
forming a gate structure of the first transistor and a gate structure of the second transistor surrounding the fin structure of the substrate, wherein the source/drain and the gate structure of the first transistor are arranged along a horizontal direction, and the source/drain and the gate structure of the second transistor are arranged along the horizontal direction;
forming a source/drain of a third transistor, a source/drain of a fourth transistor, and a second semiconductive component in the fin structure of the substrate at a second elevation, wherein the second semiconductive component is adjacent to the source/drain of the third transistor, and the second elevation is different from the first elevation;
forming a gate structure of the third transistor and a gate structure of the fourth transistor surrounding the fin structure of the substrate,
wherein the source/drain and the gate structure of the third transistor are arranged along the horizontal direction, the source/drain and the gate structure of the fourth transistor are arranged along the horizontal direction, the second transistor is vertically aligned with the third transistor, the first semiconductive component is vertically aligned with the source/drain of the fourth transistor, the second semiconductive component is vertically aligned with the source/drain of the first transistor, and a gate structure between the second semiconductive component and the source/drain of the third transistor is absent.
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