US 11,894,382 B2
Set of integrated standard cells
Olivier Weber, Grenoble (FR); and Christophe Lecocq, Varces (FR)
Assigned to STMicroelectronics France, Montrouge (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics France, Montrouge (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Dec. 7, 2021, as Appl. No. 17/544,665.
Claims priority of application No. 2013447 (FR), filed on Dec. 17, 2020.
Prior Publication US 2022/0199648 A1, Jun. 23, 2022
Int. Cl. H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 27/02 (2006.01); H01L 27/092 (2006.01)
CPC H01L 27/1203 (2013.01) [H01L 21/823807 (2013.01); H01L 21/84 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a silicon-on-insulator substrate;
at least a first standard cell framed by two second standard cells, the three cells being disposed adjacent to each other, each cell including:
at least two NMOS transistors and at least two PMOS transistors located in and on the silicon-on-insulator substrate, the at least two PMOS transistors of the first standard cell having a channel including silicon and germanium, the at least two NMOS transistors of each second standard cell having a silicon channel and a threshold voltage different in absolute value from a threshold voltage of the at least two PMOS transistors of the first standard cell.