CPC H01L 27/1203 (2013.01) [H01L 21/823807 (2013.01); H01L 21/84 (2013.01); H01L 27/0207 (2013.01); H01L 27/092 (2013.01)] | 12 Claims |
1. An integrated circuit, comprising:
a silicon-on-insulator substrate;
at least a first standard cell framed by two second standard cells, the three cells being disposed adjacent to each other, each cell including:
at least two NMOS transistors and at least two PMOS transistors located in and on the silicon-on-insulator substrate, the at least two PMOS transistors of the first standard cell having a channel including silicon and germanium, the at least two NMOS transistors of each second standard cell having a silicon channel and a threshold voltage different in absolute value from a threshold voltage of the at least two PMOS transistors of the first standard cell.
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