US 11,894,379 B2
Semiconductor devices and method of manufacturing the same
Jung-Gil Yang, Hwaseong-si (KR); Geum-Jong Bae, Suwon-si (KR); Dong-Il Bae, Seongnam-si (KR); Seung-Min Song, Hwaseong-si (KR); and Woo-Seok Park, Ansan-si (KR)
Assigned to Samsung Electronics Co., Ltd.
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 20, 2022, as Appl. No. 17/844,435.
Application 17/844,435 is a continuation of application No. 17/037,807, filed on Sep. 30, 2020, granted, now 11,367,723.
Application 17/037,807 is a continuation of application No. 16/534,070, filed on Aug. 7, 2019, granted, now 10,923,476, issued on Feb. 16, 2021.
Application 16/534,070 is a continuation of application No. 15/830,981, filed on Dec. 4, 2017, granted, now 10,431,585, issued on Oct. 1, 2019.
Claims priority of application No. 10-2016-0172883 (KR), filed on Dec. 16, 2016.
Prior Publication US 2022/0328483 A1, Oct. 13, 2022
Int. Cl. H01L 27/092 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 29/41 (2006.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/165 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01)
CPC H01L 27/0924 (2013.01) [H01L 21/82385 (2013.01); H01L 21/823456 (2013.01); H01L 21/823468 (2013.01); H01L 21/823864 (2013.01); H01L 27/088 (2013.01); H01L 27/092 (2013.01); H01L 29/0669 (2013.01); H01L 29/0673 (2013.01); H01L 29/413 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 29/66772 (2013.01); H01L 29/775 (2013.01); H01L 29/78696 (2013.01); H01L 21/823412 (2013.01); H01L 21/823807 (2013.01); H01L 29/0646 (2013.01); H01L 29/0653 (2013.01); H01L 29/165 (2013.01); H01L 29/20 (2013.01); H01L 29/42392 (2013.01); H01L 29/7853 (2013.01); H01L 2924/13086 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,
wherein the first transistor comprises:
a plurality of first channel regions being spaced apart from each other in a first direction perpendicular to a top surface of the substrate;
a first gate electrode surrounding the plurality of first channel regions;
a first external insulating spacer on upper sidewalls of the first gate electrode,
a first source/drain region connected to an edge of the plurality of first channel regions, the first source/drain region contacting the first external insulating spacer, the first source/drain region including stacking faults or dislocations therein; and
a plurality of inner-insulating spacers between the first gate electrode and the first source/drain region and between two adjacent ones of the plurality of first channel regions, the plurality of inner-insulating spacers having a curved sidewall facing the first gate electrode,
the second transistor comprises:
a plurality of second channel regions being spaced apart from each other in the first direction;
a second gate electrode surrounding the plurality of second channel regions;
a second external insulating spacer on upper sidewalls of the second gate electrode; and
a second source/drain region connected to an edge of the plurality of second channel regions, the second source/drain region contacting the second external insulating spacer, the second source/drain region including a plurality of protrusion portions facing the second gate electrode, the plurality of protrusion portions being disposed between two adjacent ones of the plurality of second channel regions, and
the first gate electrode includes a plurality of first sub-gate electrodes between two adjacent ones of the plurality of first channel regions, each of the plurality of first sub-gate electrodes includes a tail portion at an upper edge and a lower edge of the first sub-gate electrodes, the tail portion conforms to a shape of the curved sidewall of the plurality of inner-insulating spacers,
wherein the second gate electrode includes a plurality of second sub-gate electrodes between two adjacent second channel regions of the plurality of second channel regions, and
wherein a separation distance between the first source/drain region and the plurality of first sub-gate electrodes is greater than a separation distance between the second source/drain region and the plurality of second sub-gate electrodes.