US 11,894,374 B2
Semiconductor structure and manufacturing method thereof
Wenli Zhao, Hefei (CN); and Jie Bai, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 19, 2022, as Appl. No. 17/648,314.
Application 17/648,314 is a continuation of application No. PCT/CN2021/117419, filed on Sep. 9, 2021.
Claims priority of application No. 202110813115.2 (CN), filed on Jul. 19, 2021.
Prior Publication US 2023/0015200 A1, Jan. 19, 2023
Int. Cl. H01L 27/092 (2006.01); H01L 21/8238 (2006.01)
CPC H01L 27/0922 (2013.01) [H01L 21/823842 (2013.01); H01L 21/823864 (2013.01); H01L 27/092 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising a substrate, and an N-channel metal-oxide semiconductor (NMOS) transistor and a P-channel metal-oxide semiconductor (PMOS) transistor that are located on the substrate, wherein
the NMOS transistor comprises:
a first dielectric layer, located on the substrate;
a first work function layer, located on the first dielectric layer; and
a first conductive layer, located on the first work function layer; and
the PMOS transistor comprises:
a second dielectric layer, located on the substrate;
a second work function layer, located on the second dielectric layer; and
a second conductive layer, located on the second work function layer;
the first work function layer is provided with a first sidewall isolation layer on a side facing the second work function layer,
the second work function layer is provided with a second sidewall isolation layer on a side facing the first work function layer; and
the first sidewall isolation layer is located below the second sidewall isolation layer.