| CPC H01L 27/0886 (2013.01) [H01L 21/823431 (2013.01); H01L 21/823481 (2013.01)] | 20 Claims |
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1. A semiconductor device, comprising:
a substrate;
a plurality of gate structures that are spaced apart from each other in a first direction on the substrate, the plurality of gate structures extending in a second direction intersecting the first direction, each gate structure of the plurality of gate structures including a gate electrode and a gate capping pattern on the gate electrode;
a plurality of source/drain patterns on opposite sides of each gate structure of the plurality of gate structures;
a plurality of first isolation patterns that respectively penetrate adjacent gate structures of the plurality of gate structures; and
a second isolation pattern that extends in the second direction and between adjacent source/drain patterns of the plurality of source/drain patterns, and penetrates at least one gate structure of the plurality of gate structures,
wherein:
each first isolation pattern of the plurality of first isolation patterns separates two gate structures of the plurality of gate structures such that the two gate structures of the plurality of gate structures are spaced apart from each other in the second direction,
the plurality of first isolation patterns are aligned with each other along the first direction, and
top surfaces of the plurality of first isolation patterns and a top surface of the second isolation pattern are each located at a level the same as or higher than a level of a top surface of the gate capping pattern of each gate structure of the plurality of gate structures.
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