US 11,894,367 B2
Integrated circuit including dipole incorporation for threshold voltage tuning in transistors
Lung-Kun Chu, Hsinchu (TW); Mao-Lin Huang, Hsinchu (TW); Chung-Wei Hsu, Hsinchu (TW); Jia-Ni Yu, Hsinchu (TW); Kuo-Cheng Chiang, Hsinchu (TW); Kuan-Lun Cheng, Hsinchu (TW); and Chih-Hao Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 8, 2021, as Appl. No. 17/370,843.
Prior Publication US 2023/0010502 A1, Jan. 12, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01)
CPC H01L 27/0883 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823462 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;
depositing a first interfacial dielectric layer on the first semiconductor nanosheets;
depositing a dipole-inducing layer on the first interfacial dielectric layer;
depositing a first high-K dielectric layer on the dipole-inducing layer after depositing the dipole-inducing layer such that the dipole inducing layer is positioned between the first interfacial dielectric layer and the first high-K dielectric layer; and
forming a dipole layer from the dipole-inducing layer and at least one of high-K dielectric layer and the interfacial dielectric layer on the first semiconductor nanosheets by performing a thermal anneal process.