CPC H01L 27/0883 (2013.01) [H01L 21/823412 (2013.01); H01L 21/823462 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] | 20 Claims |
1. A method, comprising:
forming a plurality of first semiconductor nanosheets corresponding to channel regions of a first gate all around transistor;
depositing a first interfacial dielectric layer on the first semiconductor nanosheets;
depositing a dipole-inducing layer on the first interfacial dielectric layer;
depositing a first high-K dielectric layer on the dipole-inducing layer after depositing the dipole-inducing layer such that the dipole inducing layer is positioned between the first interfacial dielectric layer and the first high-K dielectric layer; and
forming a dipole layer from the dipole-inducing layer and at least one of high-K dielectric layer and the interfacial dielectric layer on the first semiconductor nanosheets by performing a thermal anneal process.
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