US 11,894,359 B2
Distributed semiconductor die and package architecture
Wilfred Gomes, Portland, OR (US); Mark T. Bohr, Aloha, OR (US); Rajesh Kumar, Portland, OR (US); Robert L. Sankman, Phoenix, AZ (US); Ravindranath V. Mahajan, Chandler, AZ (US); and Wesley D. McCullough, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jan. 12, 2022, as Appl. No. 17/574,485.
Application 16/902,123 is a division of application No. 15/869,637, filed on Jan. 12, 2018, granted, now 10,685,947, issued on Jun. 16, 2020.
Application 17/574,485 is a continuation of application No. 16/902,123, filed on Jun. 15, 2020, granted, now 11,257,804.
Prior Publication US 2022/0139896 A1, May 5, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 25/18 (2023.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 23/522 (2006.01); H01L 25/16 (2023.01); H01L 25/065 (2023.01); H01L 23/498 (2006.01)
CPC H01L 25/18 (2013.01) [H01L 23/481 (2013.01); H01L 23/522 (2013.01); H01L 23/5383 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 25/0652 (2013.01); H01L 25/16 (2013.01); H01L 25/50 (2013.01); H01L 23/49816 (2013.01); H01L 2924/1432 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first plurality of conductors on an upper surface of a base die;
forming a second plurality of conductors on the upper surface of the base die, wherein:
each of the first plurality of conductors is disposed on the upper surface of the base die and is spaced apart from the remaining first plurality of conductors;
each of the second plurality of conductors is disposed on the upper surface of the base die and is spaced apart from the remaining second plurality of conductors; and
each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors on the upper surface of the base die, the first plurality of conductors and the second plurality of conductors conductively coupled to circuitry included in the base die; and
conductively coupling each of a plurality of cores to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors, wherein each of the plurality of cores comprises processor core circuitry.
 
13. An apparatus, comprising:
a first plurality of conductors on an upper surface of a base semiconductor die;
a second plurality of conductors on the upper surface of the base semiconductor die, wherein:
each of the first plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining first plurality of conductors;
each of the second plurality of conductors is disposed on the upper surface of the base semiconductor die and is spaced apart from the remaining second plurality of conductors; and
each of the first plurality of conductors intersects and conductively couples to at least one of the second plurality of conductors on the upper surface of the base semiconductor die, the first plurality of conductors and the second plurality of conductors conductively coupled to circuitry included in the base semiconductor die; and
each of a plurality of cores conductively coupled to a node formed by an intersection of one of the first plurality of conductors with one of the second plurality of conductors, wherein each of the plurality of cores comprises processor core circuitry.