US 11,894,341 B2
Semiconductor package with through vias and stacked redistribution layers and manufacturing method thereof
Tsung-Ding Wang, Tainan (TW); Yen-Fu Su, Hsinchu (TW); Hao-Cheng Hou, Hsinchu (TW); Jung-Wei Cheng, Hsinchu (TW); Chien-Hsun Lee, Hsin-chu County (TW); and Hsin-Yu Pan, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Feb. 2, 2021, as Appl. No. 17/164,851.
Application 17/164,851 is a continuation in part of application No. 16/869,596, filed on May 8, 2020, granted, now 11,270,921.
Claims priority of provisional application 63/073,460, filed on Sep. 2, 2020.
Claims priority of provisional application 62/967,594, filed on Jan. 30, 2020.
Prior Publication US 2021/0242172 A1, Aug. 5, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/683 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/50 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06586 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a semiconductor die, comprising a contact post;
an encapsulant, encapsulating the semiconductor die;
a first dielectric layer, extending on the encapsulant and the semiconductor die;
a through via, extending through the first dielectric layer and having one end contacting the contact post of the semiconductor die;
an extension pad disposed on the first dielectric layer and contacting an opposite end of the through via with respect to the contact post, wherein the extension pad has an elongated shape, a first end of the extension pad overlaps with the contact post and the through via, and a second end of the extension pad overlaps with the encapsulant;
a second dielectric layer, disposed on the first dielectric layer and the extension pad; and
a routing via, extending through the second dielectric layer to contact the second end of the extension pad.