US 11,894,328 B2
Semiconductor device with edge-protecting spacers over bonding pad
Jung-Hsing Chien, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 24, 2022, as Appl. No. 17/751,982.
Application 17/751,982 is a division of application No. 16/678,134, filed on Nov. 8, 2019.
Prior Publication US 2022/0285300 A1, Sep. 8, 2022
Int. Cl. H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/7682 (2013.01); H01L 21/76885 (2013.01); H01L 23/5226 (2013.01); H01L 23/53295 (2013.01); H01L 24/03 (2013.01); H01L 24/13 (2013.01); H01L 29/41725 (2013.01); H01L 29/4236 (2013.01); H01L 2224/0217 (2013.01); H01L 2224/0219 (2013.01); H01L 2224/02181 (2013.01); H01L 2224/02185 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/03019 (2013.01); H01L 2224/0391 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05007 (2013.01); H01L 2224/05573 (2013.01); H01L 2224/10135 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a bonding pad disposed over a semiconductor substrate;
a first spacer disposed over a top surface of the bonding pad;
a dielectric liner disposed between the first spacer and the bonding pad;
a dielectric layer between the bonding pad and the semiconductor substrate, wherein the dielectric layer includes silicon-rich oxide;
a conductive bump disposed over the bonding pad and covering the first spacer and the dielectric liner, wherein the conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad;
a second spacer disposed over a sidewall of the bonding pad and conformally covering the first spacer;
a first passivation layer covering the second spacer, wherein the first spacer is in direct contact with the first passivation layer; and
a second passivation layer between the first passivation layer and the bonding pad, wherein the second spacer is covered by the second passivation layer, and a portion of the conductive bump is surrounded by the first passivation layer and the second passivation layer.