US 11,894,310 B2
Fan-out semiconductor package
Myung Sam Kang, Hwaseong-si (KR); Ki Ju Lee, Seoul (KR); Young Chan Ko, Seoul (KR); Jeong Seok Kim, Cheonan-si (KR); and Bong Ju Cho, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Mar. 8, 2021, as Appl. No. 17/194,438.
Claims priority of application No. 10-2020-0094148 (KR), filed on Jul. 29, 2020.
Prior Publication US 2022/0037259 A1, Feb. 3, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/367 (2006.01)
CPC H01L 23/5389 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3128 (2013.01); H01L 23/367 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/552 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/214 (2013.01); H01L 2924/3025 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A fan-out semiconductor package, comprising:
a first redistribution layer;
a first semiconductor chip on the first redistribution layer;
an interconnector on the first redistribution layer and spaced apart from the first semiconductor chip;
a molded layer covering the interconnector and side surfaces of the first semiconductor chip; and
a second redistribution layer on the molded layer,
wherein:
the interconnector includes a metal ball that has a full spherical shape and is electrically connected to the first redistribution layer,
the second redistribution layer includes a first line wiring, and a first via electrically connected to the first line wiring,
the first via is connected to the interconnector,
a part of the first via is in the molded layer,
the first redistribution layer includes an insulating layer, a second line wiring, and a second via that penetrates the insulating layer and is electrically connected to the second line wiring,
the second via is connected to the interconnector,
an interface between the first via and the interconnector is a curved surface such that the first via has a rounded concavity that is complementary to the full spherical shape of the interconnector, and
an interface between the second via and the interconnector is a curved surface such that the second via has a rounded concavity that is complementary to the full spherical shape of the interconnector.