US 11,894,303 B2
Circuit wiring techniques for stacked transistor structures
Dongbing Shao, Briarcliff Manor, NY (US); Chen Zhang, Guilderland, NY (US); Zheng Xu, Wappingers Falls, NY (US); and Tenko Yamashita, Schenectady, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Dec. 22, 2020, as Appl. No. 17/130,164.
Application 17/130,164 is a division of application No. 16/296,502, filed on Mar. 8, 2019, granted, now 10,950,545.
Prior Publication US 2021/0111121 A1, Apr. 15, 2021
Int. Cl. H01L 23/528 (2006.01); H01L 21/822 (2006.01); H01L 23/50 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01); H10B 41/20 (2023.01); H10B 51/20 (2023.01)
CPC H01L 23/5286 (2013.01) [H01L 21/8221 (2013.01); H01L 21/823475 (2013.01); H01L 21/823871 (2013.01); H01L 23/50 (2013.01); H01L 27/092 (2013.01); H10B 41/20 (2023.02); H10B 51/20 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method of forming a semiconductor structure comprising:
forming first and second field-effect transistors of a first type at a first vertical level of the semiconductor structure;
forming third and fourth field-effect transistors of a second type at a second vertical level of the semiconductor structure over the first vertical level of the semiconductor structure;
forming a first gate structure shared between the first and second field-effect transistors at the first vertical level;
forming a second gate structure shared between the third and fourth field-effect transistors at the second vertical level; and
forming a gate contact shared by the first and second gate structures;
wherein the first, second, third and fourth field-effect transistors provide a three-dimensional stacked transistor structure; and
wherein the first and second gate structures are vertically aligned with another in a layout of the three-dimensional stacked transistor structure between source drain/regions of the first, second, third and fourth field-effect transistors.