US 11,894,300 B2
Semiconductor memory device and method of manufacturing semiconductor memory device
Nam Jae Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 20, 2021, as Appl. No. 17/380,632.
Claims priority of application No. 10-2020-0150833 (KR), filed on Nov. 12, 2020; and application No. 10-2021-0022705 (KR), filed on Feb. 19, 2021.
Prior Publication US 2022/0148961 A1, May 12, 2022
Int. Cl. H01L 23/528 (2006.01); H01L 23/00 (2006.01); H01L 29/417 (2006.01); H10B 43/27 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 24/80 (2013.01); H01L 29/41766 (2013.01); H10B 43/27 (2023.02); H01L 2224/80895 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a source structure;
a stacked conductive layer overlapping with the source structure;
a first select conductive layer and a second select conductive layer disposed between the source structure and the stacked conductive layer;
a stacked insulating layer disposed between the first select conductive layer and the stacked conductive layer and between the second select conductive layer and the stacked conductive layer;
a first slit structure and a second slit structure passing through the stacked conductive layer and the stacked insulating layer; and
a separation insulating structure passing through the source structure,
wherein the first and second slit structures and the separation insulating structure are disposed between the first select conductive layer and the second select conductive layer, and
wherein the separation insulating structure is disposed between the first slit structure and the second slit structure.