US 11,894,299 B2
Conductive traces in semiconductor devices and methods of forming same
Chao-Wen Shih, Zhubei (TW); Chen-Hua Yu, Hsinchu (TW); Han-Ping Pu, Taichung (TW); Hsin-Yu Pan, Taipei (TW); Hao-Yi Tsai, Hsinchu (TW); and Sen-Kuei Hsu, Kaohsiung (TW)
Assigned to TAIWAN SEMICONDUCTOR LTD, Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Mar. 1, 2021, as Appl. No. 17/188,787.
Application 15/595,531 is a division of application No. 14/688,862, filed on Apr. 16, 2015, granted, now 9,653,406, issued on May 16, 2017.
Application 17/188,787 is a continuation of application No. 15/595,531, filed on May 15, 2017, granted, now 10,937,734.
Prior Publication US 2021/0183760 A1, Jun. 17, 2021
Int. Cl. H01L 23/52 (2006.01); H01L 23/525 (2006.01); H01L 23/552 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/29 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01)
CPC H01L 23/525 (2013.01) [H01L 21/56 (2013.01); H01L 23/293 (2013.01); H01L 23/3192 (2013.01); H01L 23/5225 (2013.01); H01L 23/5329 (2013.01); H01L 23/552 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/06 (2013.01); H01L 24/11 (2013.01); H01L 24/14 (2013.01); H01L 21/76807 (2013.01); H01L 21/76816 (2013.01); H01L 21/76885 (2013.01); H01L 23/5286 (2013.01); H01L 24/13 (2013.01); H01L 2224/0348 (2013.01); H01L 2224/03462 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05009 (2013.01); H01L 2224/05022 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/05572 (2013.01); H01L 2224/11622 (2013.01); H01L 2224/13022 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16104 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for forming a semiconductor device comprising:
forming a first insulating layer over a substrate, wherein the first insulating layer is a photosensitive material;
exposing a first portion and a second portion of the first insulating layer in a first exposure process;
exposing a third portion of the first insulating layer in a second exposure process, wherein the third portion does not overlap the first portion and the second portion;
after exposing the first portion, the second portion, and the third portion, removing the first portion, the second portion, and the third portion to form a first recess, a second recess, and a third recess, respectively, wherein the third recess has a different depth than the first recess and the second recess;
forming a conductive material in the first recess, the second recess, and the third recess to form a first conductive line in the first recess, a second conductive line in the second recess, and a third conductive line in the third recess; and
depositing a second insulating layer over the first insulating layer.