US 11,894,279 B2
Semiconductor stress monitoring structure and semiconductor chip
Chien-Mao Chen, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Jul. 29, 2022, as Appl. No. 17/816,294.
Application 17/816,294 is a continuation of application No. 17/070,237, filed on Oct. 14, 2020, granted, now 11,456,223.
Prior Publication US 2022/0367300 A1, Nov. 17, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 21/66 (2006.01); H01L 23/528 (2006.01)
CPC H01L 22/32 (2013.01) [H01L 23/528 (2013.01); H01L 23/5226 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor stress monitoring structure, comprising:
a substrate;
a plurality of first conductive segments over the substrate, arranged parallel to each other;
a plurality of second conductive segments arranged below the plurality of first conductive segments and parallel to each other, wherein the plurality of first conductive segments and the plurality of second conductive segments extend in the same direction; and
a sensing structure proximate to the substrate, configured to respond to a stress caused by the first conductive segments and the second conductive segments and generate a monitoring signal.