US 11,894,276 B2
Multiple gate field-effect transistors having various gate oxide thicknesses and methods of forming the same
Chih-Wei Lee, New Taipei (TW); Wen-Hung Huang, Hsinchu (TW); Kuo-Feng Yu, Hsinchu County (TW); Jian-Hao Chen, Hsinchu (TW); Hsueh-Ju Chen, Taipei (TW); and Zoe Chen, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Aug. 30, 2021, as Appl. No. 17/461,849.
Prior Publication US 2023/0061018 A1, Mar. 2, 2023
Int. Cl. H01L 21/8238 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/06 (2006.01); H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823857 (2013.01) [H01L 21/31105 (2013.01); H01L 21/823412 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823462 (2013.01); H01L 21/823821 (2013.01); H01L 27/088 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
11. A method, comprising:
forming a plurality of first suspended layers in a first fin and a plurality of second suspended layers in a second fin;
forming a first interfacial layer wrapping around the first suspended layers in the first fin and a second interfacial layer wrapping around the second suspended layers in the second fin;
forming a first high-k dielectric layer wrapping around the first interfacial layer and a second high-k dielectric layer wrapping around the second interfacial layer;
depositing a metal layer wrapping around the first and second high-k dielectric layers;
removing the metal layer from the first high-k dielectric layer;
performing an annealing process, wherein during the annealing process, oxygen in an ambient environment is driven through the metal layer, the second high-k dielectric layer, and the second interfacial layer and arrives at an outer portion of the second suspended layers, such that the outer portion of the second suspended layers is converted to an oxide layer; and
depositing a first gate electrode layer wrapping around the first high-k dielectric layer and a second gate electrode layer wrapping around the second high-k dielectric layer.