US 11,894,275 B2
FinFET device having oxide region between vertical fin structures
Kuo-Cheng Ching, Hsinchu County (TW); and Ying-Keung Leung, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 26, 2022, as Appl. No. 17/874,191.
Application 15/955,317 is a division of application No. 14/803,260, filed on Jul. 20, 2015, granted, now 9,953,881, issued on Apr. 24, 2018.
Application 17/874,191 is a continuation of application No. 16/717,367, filed on Dec. 17, 2019, granted, now 11,410,887.
Application 16/717,367 is a continuation of application No. 15/955,317, filed on Apr. 17, 2018, granted, now 10,522,416, issued on Dec. 31, 2019.
Prior Publication US 2022/0359307 A1, Nov. 10, 2022
Int. Cl. H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/84 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01)
CPC H01L 21/823807 (2013.01) [H01L 21/02123 (2013.01); H01L 21/02236 (2013.01); H01L 21/02255 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/845 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H01L 27/1211 (2013.01); H01L 29/66545 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first fin structure disposed over a substrate, the first fin structure including:
a first semiconductor material layer; and
a second semiconductor material layer disposed on the first semiconductor layer; and
a first capping layer disposed directly on the first semiconductor material layer and the second semiconductor material layer of the first fin structure;
a second capping layer disposed directly on the first capping layer of the first fin structure, wherein the first and second capping layers have different material compositions, and wherein the first capping layer extends to a greater height above the substrate than the second capping layer;
a gate dielectric layer disposed on the first capping layer; and
a gate electrode layer disposed on the gate dielectric layer.