US 11,894,247 B2
Method of manufacturing semiconductor device having hybrid bonding interface
Hsih-Yang Chiu, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on Nov. 5, 2021, as Appl. No. 17/520,556.
Application 17/520,556 is a division of application No. 16/781,377, filed on Feb. 4, 2020, granted, now 11,257,694.
Prior Publication US 2022/0059372 A1, Feb. 24, 2022
Int. Cl. H01L 21/67 (2006.01); H01L 23/528 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/67121 (2013.01) [H01L 21/67063 (2013.01); H01L 23/528 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/27 (2013.01); H01L 24/80 (2013.01); H01L 2224/02163 (2013.01); H01L 2224/0361 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80004 (2013.01)] 6 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device, comprising:
forming a dielectric layer on a substrate;
etching the dielectric layer to create a plurality of openings in the dielectric layer;
applying a sacrificial layer in at least one of the openings to cover at least a portion of the dielectric layer;
forming at least one first conductive feature in the openings where the sacrificial layer is disposed and a plurality of bases in the openings where the sacrificial layer is not disposed;
removing the sacrificial layer to form at least one air gap in the dielectric layer; and
forming a plurality of protrusions on the bases, wherein the formation of the protrusions comprises:
applying a patterned mask comprising a plurality of through holes on the dielectric layer, the first conductive feature and the bases, wherein portions of the bases are exposed through the through holes; and
performing a plating process to deposit a conductive material in the through holes.