US 11,894,243 B2
Wafer system-level fan-out packaging structure and manufacturing method
Yenheng Chen, Jiangyin (CN); and Chengchung Lin, Jiangyin (CN)
Assigned to SJ SEMICONDUCTOR (JIANGYIN) CORPORATION, Jiangyin (CN)
Filed by SJ SEMICONDUCTOR (JIANGYIN) CORPORATION, Jiangyin (CN)
Filed on Nov. 19, 2021, as Appl. No. 17/531,609.
Claims priority of application No. 202011310599.0 (CN), filed on Nov. 20, 2020; and application No. 202022718472.4 (CN), filed on Nov. 20, 2020.
Prior Publication US 2022/0165586 A1, May 26, 2022
Int. Cl. H01L 21/56 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/568 (2013.01) [H01L 23/49816 (2013.01); H01L 24/19 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/73267 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A method for manufacturing a wafer system-level fan-out packaging structure, comprising:
providing a first carrier substrate and a release layer on the first carrier substrate;
forming a redistribution layer, wherein the redistribution layer comprises a first surface and a second surface opposite to each other, wherein the first surface of the redistribution layer is placed on the release layer;
bonding a patch element to the second surface of the redistribution layer;
providing a die having a bump disposed on a front side, and bonding the front side of the die to the second surface of the redistribution layer by the bump;
forming a plastic packaging layer on the second surface of the redistribution layer, wherein the plastic packaging layer covers the patch element, a back side and side surfaces of the die;
forming a second carrier substrate, wherein the second carrier substrate is bonded to the plastic packaging layer;
bonding the second carrier substrate to the plastic packaging layer; and
removing the first carrier substrate and the release layer to expose the first surface of the redistribution layer;
forming a solder bump on the first surface of the redistribution layer; and
removing the second carrier substrate.