US 11,894,242 B2
Semiconductor package and method of manufacturing semiconductor package
Taeyoung Kim, Suwon-si (KR); Seokhong Kwon, Hwaseong-si (KR); Wonyoung Kim, Seoul (KR); and Jinchan Ahn, Hwaseong-si (KR)
Assigned to SAMSUNG ELECTRONICS CO, LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Feb. 24, 2023, as Appl. No. 18/174,576.
Application 18/174,576 is a continuation of application No. 17/212,364, filed on Mar. 25, 2021, granted, now 11,610,786.
Claims priority of application No. 10-2020-0077095 (KR), filed on Jun. 24, 2020.
Prior Publication US 2023/0223279 A1, Jul. 13, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/56 (2006.01); H01L 23/24 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/565 (2013.01) [H01L 23/24 (2013.01); H01L 21/561 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73265 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor package, the method comprising:
disposing a semiconductor chip on a substrate;
disposing the substrate in a cavity between a lower mold and an upper mold of a molding apparatus;
after disposing the substrate in the cavity, a mechanical reinforcing pattern around the semiconductor chip within the cavity such that the mechanical reinforcing pattern is suspended at a predetermined height from the substrate;
injecting a molding material into the cavity; and
curing the molding material within the cavity.