US 11,894,101 B2
Sense amplifier, memory and control method
Hsin-Cheng Su, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 10, 2022, as Appl. No. 17/647,552.
Application 17/647,552 is a continuation of application No. PCT/CN2021/107888, filed on Jul. 22, 2021.
Claims priority of application No. 202110314431.5 (CN), filed on Mar. 24, 2021.
Prior Publication US 2022/0310142 A1, Sep. 29, 2022
Int. Cl. G11C 7/06 (2006.01); G11C 7/12 (2006.01); G11C 7/10 (2006.01); G11C 7/08 (2006.01)
CPC G11C 7/12 (2013.01) [G11C 7/08 (2013.01); G11C 7/1096 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A sense amplifier, comprising:
an amplify circuit, configured to amplify a voltage difference between a bit line and a reference bit line when the sense amplifier is in an amplifying stage;
a write circuit, connected to the bit line and the reference bit line, and configured to pull the voltage difference between the bit line and the reference bit line according to data to be written into memory cells the sense amplifier is in a write stage; and
a controllable power circuit, connected to the amplify circuit, configured to provide a first voltage to the amplify circuit when the sense amplifier is in a non-write stage, and to provide a second voltage to the amplify circuit when the sense amplifier in the write stage; wherein the second voltage is less than the first voltage, and the second voltage is in positive correlation with a drive capability of the write circuit;
wherein a process of writing the data into the memory cells comprises an access stage, a sensing stage, the write stage and a recover stage; and the non-write data stage comprises the access stage, the sending stage and the recover stage.