US 11,894,098 B2
Dynamic random access memory applied to an embedded display port
Der-Min Yuan, New Taipei (TW); Yen-An Chang, Miaoli County (TW); and Wei-Ming Huang, Hsinchu County (TW)
Assigned to Etron Technology, Inc., Hsinchu (TW)
Filed by Etron Technology, Inc., Hsinchu (TW)
Filed on Mar. 25, 2021, as Appl. No. 17/213,133.
Application 17/213,133 is a continuation of application No. 16/151,347, filed on Oct. 4, 2018, granted, now 10,998,017.
Application 16/151,347 is a continuation of application No. 13/922,242, filed on Jun. 19, 2013, abandoned.
Claims priority of provisional application 61/768,406, filed on Feb. 23, 2013.
Claims priority of provisional application 61/672,287, filed on Jul. 17, 2012.
Prior Publication US 2021/0217451 A1, Jul. 15, 2021
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/10 (2006.01); G11C 11/4074 (2006.01); G06F 12/0882 (2016.01); G06F 3/06 (2006.01); G06F 12/02 (2006.01); G06F 13/42 (2006.01); G06F 12/06 (2006.01); G06F 12/0866 (2016.01); G11C 11/406 (2006.01)
CPC G11C 7/1075 (2013.01) [G11C 11/4074 (2013.01); G06F 3/061 (2013.01); G06F 3/0653 (2013.01); G06F 3/0656 (2013.01); G06F 12/0238 (2013.01); G06F 12/063 (2013.01); G06F 12/0692 (2013.01); G06F 12/0866 (2013.01); G06F 12/0882 (2013.01); G06F 13/4221 (2013.01); G06F 13/4278 (2013.01); G11C 11/40615 (2013.01); Y02D 10/00 (2018.01)] 9 Claims
OG exemplary drawing
 
1. A dynamic random access memory (DRAM), comprising:
a DRAM core cell comprised in the DRAM, wherein the DRAM core cell is supplied with a first voltage within a first voltage range to make the DRAM core cell operate at the first voltage, and the DRAM core cell is a volatile memory cell, wherein the first voltage is lower than 1.1V; and
a peripheral circuit comprised in the DRAM, wherein the peripheral circuit is electrically connected to the DRAM core cell, and the peripheral circuit is supplied with a second voltage within a second voltage range to make the peripheral circuit operate at the second voltage, wherein the second voltage is lower than 1.1V, and
wherein the DRAM core cell and the peripheral circuit are formed on a single chip, and the peripheral circuit is external to the DRAM core cell, and wherein the first voltage is different from the second voltage.