US 11,894,095 B2
Semiconductor memory device
Yuji Satoh, Kawasaki Kanagawa (JP); and Hiromitsu Komai, Kamakura Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Mar. 2, 2022, as Appl. No. 17/685,230.
Claims priority of application No. 2021-154184 (JP), filed on Sep. 22, 2021.
Prior Publication US 2023/0087689 A1, Mar. 23, 2023
Int. Cl. G11C 7/06 (2006.01); G11C 7/10 (2006.01)
CPC G11C 7/065 (2013.01) [G11C 7/106 (2013.01); G11C 7/109 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a plurality of data latch circuits that are used for input and output of data between a sense amplifier circuit and an input/output circuit; and
a data wiring that is connected to the plurality of data latch circuits, wherein
each of the data latch circuits includes
a data storage unit that temporarily stores data input and output between the sense amplifier circuit and the input/output circuit, and
at least two N-channel type MOS transistors and at least one P-channel type MOS transistor provided between the data storage unit and the data wiring, and
a common signal line is connected to gates of the at least two N-channel type MOS transistors.