CPC G11C 29/50004 (2013.01) [G11C 11/5635 (2013.01); G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/349 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 25/18 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02); G11C 2029/5004 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] | 20 Claims |
1. A fail detecting method of a memory system comprising a nonvolatile memory device and a memory controller, the fail detecting method comprising:
counting, by the memory controller, the number of erases of a word line connected to a pass transistor;
issuing a first erase command, by the memory controller, when the number of erases reaches a reference value;
applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value;
detecting, by the memory controller, a leakage current in the word line, after the applying of the first voltage; and
determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.
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