US 11,894,091 B2
Synchronized memory repair system (SRS)
Yaron Freiman, Tel-Mond (IL); Noam Jungmann, Holon (IL); Tomer Abraham Cohen, Binyamina (IL); Elazar Kachir, Tel Aviv (IL); and Hezi Shalom, Tel Aviv (IL)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Mar. 23, 2022, as Appl. No. 17/656,017.
Prior Publication US 2023/0307080 A1, Sep. 28, 2023
Int. Cl. G06F 11/00 (2006.01); G11C 29/44 (2006.01); G06F 11/16 (2006.01); G06F 11/14 (2006.01); G06F 11/20 (2006.01); G06F 11/07 (2006.01); G11C 11/418 (2006.01)
CPC G11C 29/4401 (2013.01) [G06F 11/073 (2013.01); G06F 11/0793 (2013.01); G06F 11/141 (2013.01); G06F 11/1666 (2013.01); G06F 11/2043 (2013.01); G11C 11/418 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A computer system for processing synchronized memory repairs comprising:
a memory array comprising:
a plurality of memory rows, the plurality of memory rows comprising a plurality of functioning memory rows, at least one faulty memory row, and a plurality of memory repair rows; and
a plurality of wordlines, wherein each wordline of the plurality of wordlines:
is communicatively and operably coupled to one memory row of the plurality of memory rows; and
an integrated memory decoder communicatively and operably coupled to the memory array, the integrated memory decoder comprising logic circuitry configured to execute operation of the plurality of functioning memory rows, the integrated memory decoder further configured to:
execute memory row repair operations directed toward the faulty memory row, comprising:
identifying a memory repair row from the plurality of memory repair rows to operationally replace the faulty memory row;
creating a multiple hot state within the integrated memory decoder;
activating a wordline of the identified memory repair row through the multiple hot state; and
executing one or more memory operations on the identified memory repair row through the integrated memory decoder.