US 11,894,090 B2
Selective power-on scrub of memory units
Zhenlei Shen, Milpitas, CA (US); Tingjun Xie, Milpitas, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 6, 2023, as Appl. No. 18/117,583.
Application 18/117,583 is a continuation of application No. 17/394,232, filed on Aug. 4, 2021, granted, now 11,626,182.
Prior Publication US 2023/0207041 A1, Jun. 29, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 29/00 (2006.01); G11C 29/42 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 13/00 (2006.01); G11C 29/04 (2006.01)
CPC G11C 29/42 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2029/0407 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of groups of managed units; and
a processing device operatively coupled to the memory device, the processing device to, during power on of the memory device, perform operations comprising:
causing a read operation to be performed at a subset of a group of managed units;
determining a bit error rate related to data read from the subset of the group of managed units, wherein the bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states; and
in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.