CPC G11C 29/42 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 2029/0407 (2013.01)] | 20 Claims |
1. A system comprising:
a memory device comprising a plurality of groups of managed units; and
a processing device operatively coupled to the memory device, the processing device to, during power on of the memory device, perform operations comprising:
causing a read operation to be performed at a subset of a group of managed units;
determining a bit error rate related to data read from the subset of the group of managed units, wherein the bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states; and
in response to the bit error rate satisfying a threshold criterion, causing a rewrite of the data stored at the group of managed units.
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