US 11,894,089 B2
Memory with error checking and correcting unit
Weibing Shang, Hefei (CN); Hongwen Li, Hefei (CN); Liang Zhang, Hefei (CN); Kangling Ji, Hefei (CN); Sungsoo Chi, Hefei (CN); Daoxun Wu, Hefei (CN); and Ying Wang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 22, 2021, as Appl. No. 17/481,413.
Application 17/481,413 is a continuation of application No. PCT/CN2021/106114, filed on Jul. 13, 2021.
Claims priority of application No. 202010988666.8 (CN), filed on Sep. 18, 2020.
Prior Publication US 2022/0093201 A1, Mar. 24, 2022
Int. Cl. G11C 29/10 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/026 (2013.01); G11C 29/10 (2013.01); G11C 29/4401 (2013.01); G11C 2029/1204 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and
a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
wherein each of the U half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit; or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.