US 11,894,087 B2
Test circuit
MinNa Li, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/440,114
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Jul. 7, 2021, PCT No. PCT/CN2021/105067
§ 371(c)(1), (2) Date Sep. 16, 2021,
PCT Pub. No. WO2022/166107, PCT Pub. Date Aug. 11, 2022.
Claims priority of application No. 202110160891.7 (CN), filed on Feb. 5, 2021.
Prior Publication US 2023/0197179 A1, Jun. 22, 2023
Int. Cl. G11C 29/38 (2006.01); G11C 29/18 (2006.01)
CPC G11C 29/38 (2013.01) [G11C 29/18 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A test circuit comprising:
an input terminal, a processing circuit and an output terminal;
wherein the input terminal receives an input signal, wherein the input signal comprises a test command to instruct a test target circuit module and an address of a target circuit module;
wherein the processing circuit is configured to determine a test mode signal according to the test command and the address of the target circuit module, wherein the test mode signal carries a test type, wherein the test mode signal triggers the target circuit module to perform a test according to the test type; and
wherein the output terminal sends the test mode signal to the target circuit module according to the address of the target circuit module;
wherein the processing circuit comprises:
a first address latch, a second address latch, a command logic circuit, a control logic circuit, a test decoding circuit and a slave latch;
wherein the first address latch receives a first internal address and outputs a first internal delay address;
wherein the command logic circuit receives the test command and a second internal address, and outputs a test mode command; and
wherein the second address latch receives a third internal address and the test mode command, and outputs a third internal delay address;
wherein the control logic circuit is configured to receive the first internal delay address and the test mode command, and outputs a test mode enable active signal and a test mode enable slave signal;
wherein the test decoding circuit is configured to receive the first internal delay address and the third internal delay address, and outputs a decoding signal; and
wherein the slave latch receives the third internal address and the test mode enable slave signal, and outputs a slave address.