US 11,894,085 B2
Memory section selection for a memory built-in self-test
Scott E. Schaefer, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jun. 16, 2022, as Appl. No. 17/807,303.
Claims priority of provisional application 63/365,642, filed on Jun. 1, 2022.
Prior Publication US 2023/0395173 A1, Dec. 7, 2023
Int. Cl. G11C 29/12 (2006.01); G06F 11/10 (2006.01)
CPC G11C 29/12 (2013.01) [G06F 11/1044 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory sections; and
one or more components configured to: read a first set of bits stored in a test control mode register of the memory device;
identify a test mode, for performing a memory built-in self-test, based on the first set of bits;
read a second set of bits stored in a section identifier mode register of the memory device;
identify, based on the second set of bits indicating one or more memory sections of the plurality of memory sections, a subset of the plurality of the memory sections for which the memory built-in self-test is to be performed, the subset comprising the one or more memory sections; and
perform, based on the test mode, the memory built-in self-test for the one or more memory sections indicated by the second set of bits.