US 11,894,081 B2
EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures
Yu-Chung Lien, San Jose, CA (US); Xue Bai Pitner, Sunnyvale, CA (US); and Ken Oowada, Fujisawa (JP)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Mar. 2, 2022, as Appl. No. 17/685,113.
Prior Publication US 2023/0282295 A1, Sep. 7, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/3495 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for programming a target memory cell of a memory array of a non-volatile memory system, comprising:
determining a total number of erase/programming (EP) cycles applied previously to the target memory cell;
comparing the total number of erase/programming (EP) cycles to a threshold value; and
applying an asymmetric programming scheme as a result of determining that the total number of erase/programming (EP) cycles does not exceed a threshold value; and
applying a symmetric programming scheme as a result of determining that the total number of erase/programming (EP) cycles exceeds the threshold value.