US 11,894,078 B2
Accessing a multi-level memory cell
Karthik Sarpatwari, Boise, ID (US); Xuan-Anh Tran, Boise, ID (US); Jessica Chen, Boise, ID (US); Jason A. Durand, Boise, ID (US); Nevil N. Gajera, Meridian, ID (US); and Yen Chun Lee, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 26, 2022, as Appl. No. 17/825,941.
Application 17/825,941 is a continuation of application No. 16/926,556, filed on Jul. 10, 2020, granted, now 11,355,209.
Prior Publication US 2022/0284973 A1, Sep. 8, 2022
Int. Cl. G11C 16/30 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
applying a plurality of voltages as part of a pre-read portion of a read operation;
applying a first read voltage to a memory cell as part of a read portion of the read operation based at least in part on applying the plurality of voltages;
identifying a second read voltage that comprises a different polarity than the first read voltage based at least in part on applying the first read voltage; and
identifying a logic state stored by the memory cell based at least in part on applying the first read voltage and the second read voltage.