CPC G11C 16/3459 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01)] | 20 Claims |
1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines and disposed in memory holes and configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes organized in rows grouped in a plurality of strings; and
a control means coupled to the plurality of word lines and the memory holes and configured to:
program the memory cells connected to one of the plurality of word lines and associated with a first one of the plurality of strings in a program operation and acquire a smart verify programming voltage in a smart verify operation including a plurality of smart verify loops, and
discard the smart verify programming voltage and determine another smart verify programming voltage in another smart verify operation on the memory cells associated with a second one of the plurality of strings in response to a quantity of the plurality of smart verify loops needed to complete programming of the memory cells associated with the first one of the plurality of strings being outside a predetermined threshold criteria.
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