US 11,894,072 B2
Two-side staircase pre-charge in sub-block mode of three-tier non-volatile memory architecture
Jiacen Guo, Cupertino, CA (US); Xiang Yang, Santa Clara, CA (US); and Abhijith Prakash, Milpitas, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Apr. 20, 2022, as Appl. No. 17/724,769.
Prior Publication US 2023/0343400 A1, Oct. 26, 2023
Int. Cl. G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 11/56 (2006.01); G11C 16/10 (2006.01); G11C 16/04 (2006.01)
CPC G11C 16/3427 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells each connected to one of a plurality of word lines and disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states; and
a control means coupled to the plurality of word lines and the strings and configured to:
ramp a voltage applied to a selected one of the plurality of word lines from a verify voltage to a reduced voltage during at least one program-verify portion of at least one program loop of a program operation, and
successively ramp voltages applied to each of a plurality of neighboring ones of the plurality of word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the plurality of word lines immediately adjacent the selected one of the plurality of word lines and progressing to others of the plurality of neighboring ones of the plurality of word lines disposed increasingly remotely from the selected one of the plurality of word lines during the at least one program-verify portion of the at least one program loop of the program operation.