US 11,894,070 B2
Semiconductor memory device
Takeshi Hioka, Machida (JP); Tsukasa Kobayashi, Machida (JP); Koji Kato, Yokohama (JP); Yuki Shimizu, Kamakura (JP); and Hiroshi Maejima, Tokyo (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Jan. 19, 2023, as Appl. No. 18/156,654.
Application 18/156,654 is a continuation of application No. 17/481,892, filed on Sep. 22, 2021, granted, now 11,594,285.
Application 17/481,892 is a continuation of application No. 17/103,230, filed on Nov. 24, 2020, granted, now 11,158,388, issued on Oct. 26, 2021.
Application 17/103,230 is a continuation of application No. 16/429,680, filed on Jun. 3, 2019, granted, now 10,892,020, issued on Jan. 12, 2021.
Claims priority of application No. 2018-121151 (JP), filed on Jun. 26, 2018.
Prior Publication US 2023/0154547 A1, May 18, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 16/26 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/30 (2006.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01); H10B 43/27 (2023.02); H10B 43/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
first and second memory cells;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a first bit line connected to the first memory cell;
a second bit line connected to the second memory cell;
a first sense amplifier connected to the first bit line, the first sense amplifier having a first node to determine data;
a second sense amplifier connected to the second bit line, the second sense amplifier having a second node to determine data; and
a control circuit which supplies control signals to the first sense amplifier and the second sense amplifier,
wherein in a read operation,
the control circuit supplies a first control signal to connect the first node of the first sense amplifier to the first bit line, and a second control signal to connect the second node of the second sense amplifier to the second bit line, and
a timing at which supply of the first control signal ends and a timing at which supply of the second control signal ends are different.