| CPC G11C 16/26 (2013.01) [G06F 11/1068 (2013.01); G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 11/5671 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06562 (2013.01)] | 19 Claims |
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1. A non-volatile memory device, comprising:
a control circuit configured to connect to one or more non-volatile memory cells, the control circuit configured to:
perform read operations in a first read mode, in which the control circuit is configured to:
perform a first hard bit read operation at a read level configured to determine a first hard bit value for each of one or more selected ones of the non-volatile memory cells, the first hard bit value indicating whether the memory cell is either reliably in a first data state or unreliability in a second data state;
perform a first soft bit read operation configured to generate a first soft bit value indicating a reliability value for each of the memory cells determined to be in the second data state, but not for memory cells determined to be in the first data state; and
provide the first hard bit values and the first soft bit values to an error correction code engine configured to determine data content of selected memory cells from the first hard bit values and the first soft bit values,
perform read operations in a second read mode, in which the control circuit is configured to:
perform a read operation for distinguishing between the first data state and the second data state based on only a second hard bit read value, and
store parameter values for performing the first hard bit read operation and for performing the first soft bit read operation as offsets relative to parameter values configured for performing the read operation for distinguishing between the first data state and the second data state based on only the second hard bit read value.
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