US 11,894,067 B2
Method to fix cumulative read induced drain side select gate downshift in memory apparatus with on-pitch drain side select gate
Xiang Yang, Santa Clara, CA (US); Abhijith Prakash, Milpitas, CA (US); and Shubhajit Mukherjee, San Jose, CA (US)
Assigned to SANDISK TECHNOLOGIES LLC, Addison, TX (US)
Filed by SanDisk Technologies LLC, Addison, TX (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,640.
Prior Publication US 2023/0186998 A1, Jun. 15, 2023
Int. Cl. G06F 12/00 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/32 (2006.01); G11C 16/16 (2006.01)
CPC G11C 16/26 (2013.01) [G06F 12/00 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/32 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory apparatus, comprising:
memory cells configured to retain a threshold voltage and connected to one of a plurality of word lines and arranged in strings comprising a plurality of blocks; and
a control means coupled to the plurality of word lines and the strings and configured to:
periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells, and
relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.