CPC G11C 16/14 (2013.01) [G11C 16/08 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/28 (2013.01); G11C 16/34 (2013.01); G11C 16/3409 (2013.01); G11C 16/3445 (2013.01)] | 20 Claims |
1. A memory apparatus, comprising:
memory cells connected to one of a plurality of word lines including at least one dummy word line and a plurality of data word lines and arranged in one or more strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states; and
a control means coupled to the plurality of word lines and the one or more strings and configured to:
identify ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below a predetermined detection voltage threshold following an erase operation, and
reduce threshold voltage down shifting of a semi-circle drain side select gate by selectively applying at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.
|