US 11,894,057 B2
Memory device performing program operation and method of operating the same
Jung Shik Jang, Icheon-si (KR); Dong Hun Lee, Icheon-si (KR); and Yun Sik Choi, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 12, 2021, as Appl. No. 17/373,423.
Claims priority of application No. 10-2021-0010361 (KR), filed on Jan. 25, 2021.
Prior Publication US 2022/0238161 A1, Jul. 28, 2022
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G11C 16/24 (2006.01); G11C 11/56 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01); G11C 11/56 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells;
a peripheral circuit configured to perform an incremental step pulse program (ISPP) on a selected memory cell among the plurality of memory cells to a target program state among a plurality of program states; and
control logic configured to store a program setting table on bit line step voltages corresponding to the plurality of program states, respectively, and control the peripheral circuit to perform the ISPP using a bit line voltage set based on the target program state and the program setting table,
wherein the bit line step voltages have different values from each other according to corresponding program states, respectively, in the program setting table.