US 11,894,052 B2
Compensated analog computation for an in-memory computation system
Marco Pasotti, Travaco' Siccomario (IT); Marcella Carissimi, Bergamo (IT); Alessio Antolini, Bologna (IT); Eleonora Franchi Scarselli, Bologna (IT); Antonio Gnudi, Bologna (IT); Andrea Lico, Polia (IT); and Paolo Romele, Impington (GB)
Assigned to STMicroelectronics S.r.l., Agrate Brianza (IT); and Alma Mater Studiorum—Universita' Di Bologna, Bologna (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT); and Alma Mater Studiorum-Universita' Di Bologna, Bologna (IT)
Filed on Apr. 12, 2022, as Appl. No. 17/718,908.
Prior Publication US 2023/0326524 A1, Oct. 12, 2023
Int. Cl. G11C 16/06 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0061 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0038 (2013.01)] 27 Claims
OG exemplary drawing
 
1. An in-memory computation circuit, comprising:
a memory array including a plurality of memory cells arranged in a matrix with plural rows and plural columns, the memory cells storing computational weights for an in-memory compute operation, each row including a word line connected to the memory cells of the row, and each column including a bit line connected to the memory cells of the column;
a biasing circuit for each bit line comprising:
a first transistor and second transistor having source-drain paths connected in series between the bit line and a column output;
wherein said first transistor is configured to apply a fixed reference voltage level to said bit line;
wherein said second transistor is configured as a switching circuit and controlled to turn on for a time duration corresponding to coefficient data for said in-memory compute operation; and
wherein an analog signal at the column output is dependent on the coefficient data and computational weight; and
a column combining circuit configured to combine and integrate the analog signals generated at the column outputs of the biasing circuits.