US 11,894,050 B2
Memory with a sense amplifier isolation scheme for enhancing memory read bandwidth
Hochul Lee, Los Angeles, CA (US); Anil Chowdary Kota, San Diego, CA (US); Dhvani Sheth, San Diego, CA (US); and Chulmin Jung, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Sep. 22, 2021, as Appl. No. 17/481,601.
Prior Publication US 2023/0087277 A1, Mar. 23, 2023
Int. Cl. G11C 11/419 (2006.01); G11C 11/412 (2006.01)
CPC G11C 11/419 (2013.01) [G11C 11/412 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory, comprising;
a sense amplifier configured to pre-charge a pair of sense amplifier input nodes responsive to an assertion of a sense amplifier pre-charge signal;
a self-timed memory circuit including a dummy bit line circuit configured to assert a dummy bit line output signal to trigger a de-assertion of the sense amplifier pre-charge signal;
a first plurality of columns, each column in the first plurality of columns including a pair of bit lines;
a first read column multiplexer configured to select a first selected column from the first plurality of columns responsive to an assertion of a first read multiplexer address signal to couple the pair of bit lines in the first selected column to the pair of sense amplifier input nodes; and
a first switch coupled between a node for the first read multiplexer address signal and a power supply node, wherein the first switch is configured to open in response to the assertion of the dummy bit line output signal.